The present invention relates to integrated circuits and, more particular, to improved integrated circuit contact formation. A major objective of the present invention is to reduce contact resistance between tungsten based barrier metal and underlying active semiconductor regions.
Modem technological progress has been closely identified with the increasing performance and miniaturization associated with developments in integrated circuit fabrication. Integrated circuit structures are formed by patterning negatively and positively doped regions within a semiconductor structure. On-chip circuits and external interfacing require contacts to be formed with the doped regions.
Conventionally, contacts can be formed by patterning aluminum over the doped regions. Aluminum is favored because it is highly conductive, inexpensive, and relatively easily to pattern. However, aluminum from the contact can migrate into a silicon substrate through a doped region, causing a short to the substrate. This problem can be mitigated by including silicon in the aluminum. However, contact resistance goes up, because silicon is not a good conductor. Furthermore, silicon and aluminum migration can still occur, especially during elevated temperatures.
To minimize this shorting, some processing techniques deposit a barrier layer before depositing the aluminum. One type of barrier material is titanium-tungsten. However, the effectiveness of the resulting contact is limited by the contact resistance between the titanium-tungsten and the doped regions. This contact resistance is greater for positively doped regions than for negatively doped regions; in fact, the contact between the tungsten and positively doped silicon can be non-ohmic. Contact resistance is of particular concern in CMOS (complementary metal-oxide-silicon) technology, which includes barrier metal contacts with positively doped regions as well as with negatively doped region.
This resistance can be reduced by annealing. Further improvements can be attained by using platinum silicide under the barrier metal. Platinum must be deposited and then a silicide formed. This process is complex and expensive. Subsequent high-temperature processing is limited, undesirably constraining packaging procedures. Furthermore, platinum raises contamination concerns as it can kill the minority carrier.
Furthermore, as integrated circuit devices are defined more finely, contact resistance becomes more critical. Thus, formerly adequate approaches for limiting contact resistance are becoming less adequate. What is needed is a method for further reducing contact resistance when a barrier layer is utilized.